1. Field of the Invention
The present invention relates to inter-processor communication, and more particularly, to inter-processor communication assisted by an external memory based first-in-first-out (xFIFO) apparatus.
2. Description of the Prior Art
In general, conventional basestation transceivers are connected to the basestation controllers through dedicated communication links such as T1 or E1 lines. These basestation controllers are connected to each other and also connected to other network equipments such as Serving GPRS Support Node (SGSN) or Gateway GPRS Support Node (GGSN) in General Packet Radio Service (GPRS) network. Recently, a femtocell (Home Node B) is a miniature device in the size of a CPE which functions as a combination of RNC and Home Node B and is connected through internet to the Core Network.
A femtocell baseband system-on-chip (SOC) consists of multiple Nios II embedded processor cores, as well as various hardware accelerators and peripheral interface logic. These processor cores are responsible for running many different software components, from device drivers, firmware, communication protocol stack, all the way up to the user level applications. Periodically, the different software threads need to communicate with each other, either to exchange control or data information or to synchronize with each other, to ensure that the events on different processor cores happen in the proper order and with the correct outcome. With up to concurrent 16 users incurring both voice and data traffic, the femtocell SOC demands that the inter-processor communications (IPC) between these software components be fast and efficient.
In general, typical IPC schemes used in a multi-core embedded system include message passing, shared memory, one-to-one synchronization metaphor (e.g., semaphores and signals), and N-to-one synchronization metaphor (e.g., spin-lock or test-and-set). Our hardware support for IPC is focused on the message passing method. In the message-passing IPC paradigm, a software thread does not share any common memory space with the other software thread it wishes to communicate. Instead, they communicate with each other via a simplex (one-directional) FIFO queue, for which one thread has a fixed role as the producer, and the other as the consumer. If a duplex message passing interface is required, two such FIFO queues may be employed.
Since we always have no idea beforehand about how much data should be exchanged between two different software threads or how frequently, therefore, the message FIFO between two processor cores needs to be low latency, so that the processors will not be slowed down due to frequent communication, and needs to be large-sized to avoid unnecessary coupling between the two processor cores due to FIFO fullness/emptiness. In order to achieve low access latency, an on-chip memory is typically used to provide the buffer space, whereas to provide large amount of buffer space, an off-chip memory (e.g., DRAM) is often employed for data storage.
Although the off-chip memory is much cheaper than the on-chip memory, the access latency for the off-chip memory is often much higher than that for the on-chip memory. Therefore, the need for lower access latency and the need for larger buffer space are contradictory; it is hard for the designer to select one from the off-chip memory and the on-chip memory.
Therefore, the invention provides an inter-processor communication assisting apparatus to solve the aforementioned problems.